Hiroyuki Ito, Ph.D.
Affiliation Section of Electron Devices in Division of Advanced Microdevices, Precision and Intelligence Laboratory
and
Department of Electronics and Applied Physics, Interdisciplinary Graduate School of Science and Engineering
History
  • 09/2013 - present
    Associate Professor, Department of Electronics and Applied Physics, Tokyo Institute of Technology, Yokohama, Japan.
  • 08/2013 - present
    Associate Professor, Precision and Intelligence Laboratory, Tokyo Institute of Technology, Yokohama, Japan.
  • 04/2007 - 07/2013
    Assistant Professor, Precision and Intelligence Laboratory, Tokyo Institute of Technology, Yokohama, Japan.
  • 10/2009 - 9/2010
    Researcher, Fujitsu Laboratories Ltd.
  • 08/2007
    Visiting Professor, Communications Circuits Laboratory, Corporate Technology Group, Intel.
  • 04/2006 - 03/2007
    Tokyo Tech Postdoctoral Fellow
  • 04/2006 - 03/2007
    Research Fellow (PD) of the Japan Society for the Promotion of Science.
  • 07/2006 - 12/2006
    Temporary Visiting Researcher, Communications Circuits Laboratory, Corporate Technology Group, Intel.
  • 03/2006
    Ph.D. Degree in Department of Advanced Applied Electronics, Tokyo Institute of Technology, Yokohama, Japan.
    Ph.D. Dissertation: Investigation of High-Speed Signal Transmission on Si CMOS LSI
  • 04/2004 - 03/2006
    Research Fellow (DC1) of the Japan Society for the Promotion of Science.
  • 03/2004
    M. E. Degree in Department of Advanced Applied Electronics, Tokyo Institute of Technology, Yokohama, Japan.
    M. E. Dissertation: Differential Transmission Line Structure on Si ULSI
  • 12/2002 - 2/2003
    Intern of Information Technology R&D Center (Japan), Mitsubishi Electric.
  • 03/2002
    B. E. Degree in Electronics and Mechanical Engineering, Chiba University, Chiba, Japan.
    B. E. Dissertation: System Construction for Surface Acoustic Wave Visualization
Specialty
Research on integrated circuits and harware technology to connect real space and cyberspace
  1. Sensing technology for cyber physical system
  2. Ultra low power RF transceivers
  3. CMOS/MEMS fusion circuit technology
  4. High speed signal transmission techniques for integrated circuits
Journals
  1. Atsushi Shirane, Yiming Fang, Haowei Tan, Taiki Ibe, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "RF-Powered Transceiver With an Energy and Spectral-Efficient IF-Based Quadrature Backscattering Transmitter," IEEE Journal of Solid-State Circuits, Vol. 50, No. 12, pp. 2975-2987, Dec. 2015.
  2. Sho Ikeda, Sang yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu "0.5 V 5.8 GHz highly linear current-reuse voltage-controlled oscillator with back-gate tuning technique," Japanese Journal of Applied Physics, Vol. 54, No. 4S, pp. 04DE06.1-6, Mar. 2015. (doi:10.7567/JJAP.54.04DE06)
  3. Sho Ikeda, Sang_yeop Lee, Tatsuya Kamimura, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS," IEICE Transactions on Electronics, Vol. E97-C, No. 6, pp. 495-504, Jun. 2014.
  4. Sang yeop Lee, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A Novel Direct Injection-Locked QPSK Modulator Based on Ring VCO in 180 nm CMOS," IEEE Microwave and Wireless Components Letters, Vol. 24, No. 4, pp. 269-271, Apr. 2014. (DOI: 10.1109/LMWC.2014.2299534)
  5. Motohiro Takayasu, Atsushi Shirane, Sangyeop Lee, Daisuke Yamane, Hiroyuki Ito, Xiaoyu Mi, Hiroaki Inoue, Fumihiko Nakazawa, Satoshi Ueda, Noboru Ishihara, and Kazuya Masu, "An 8-ch, 20-V Output CMOS Switching Driver with 3.3-V Power Supply for Integrated MEMS Devices Controlling," Japanese Journal of Applied Physics, vol. 53, 2014, pp. 04EE13.1-8. (Special issue on SSDM 2013) (DOI: 10.7567/JJAP.53.04EE13)
  6. Toshifumi Konishi, Daisuke Yamane, Takaaki Matsushima, Gou Motohashi, Ken Kagaya, Hiroyuki Ito, Noboru Ishihara,　Hiroshi Toshiyoshi, Katsuyuki Machida, and Kazuya Masu, "Novel Sensor Structure and its Evaluation for Integrated Complementary Metal Oxide Semiconductor Microelectromechanical Systems Accelerometer," Japanese Journal of Applied Physics (special issue on MNC 2012), vol. 52, no. 6, pp. 06GL04, June 2013.
  7. Sho Ikeda, Sang yeop Lee, Tatsuya Kamimura, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "Fractionally Injection-Locked Frequency Multiplication Technique with Multi-Phase Ring Voltage-Controlled Oscillator," Japanese Journal of Applied Physics, Vol. 52, No. 4, pp. 04CE15-1-04CE15-6, April 2013.
  8. Sang yeop Lee, Hiroyuki Ito, Shuhei Amakawa, Noboru Ishihara, and Kazuya Masu, "An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS," International Journal of Microwave Science and Technology, Vol. 2013, Article ID 584341, pp. 1-11, January 2013.
  9. Sang yeop Lee, Tatsuya Kamimura, Shin Yonezawa, Atsushi Shirane, Sho Ikeda, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A Multi-Band Quadrature Clock Generator with High-Pass-Filtered Pulse Injection Technique," IEEE Microwave and Wireless Components Letters, Vol. 23, No. 2, pp. 96-98, February 2013.
  10. Hamid Kiumarsi, Hiroyuki Ito, Kenichi Okada, Yusuke Uemichi, Yasuto Chiba, Noboru Ishihara, and Kazuya Masu, "A 60 GHz 3-dB Tandem Coupler using Offset Broadside-Coupled Lines on a Silicon Substrate," IEICE Electronics Express, Vol. 10, No. 2, pp. 20120901, January 2013.
  11. Sang yeop Lee, Hiroyuki Ito, Satoru Tanoi, Noboru Ishihara, and Kazuya Masu, "Injection-Locked Fractional Frequency Multiplier with Automatic Reference Pulse-Selection Technique," IEICE Electronics Express, Vol. 9, No. 21, pp. 1624-1629, November 2012.
  12. Sang yeop Lee, Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65nm CMOS," IEICE Transactions, Vol. E95-C, No. 10, pp. 1589-1597, October 2012.
  13. Atsushi Shirane, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "Planar Solenoidal Inductor in Radio Frequency Micro-Electro-Mechanical Systems Technology for Variable Inductor with Wide Tunable Range and High Quality Factor," Japanese Journal of Applied Physics, Vol. 51, 05EE02, pp. 1-4, May 2012.
  14. Tatsuya Kamimura, Sang yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "0.1 V 13 GHz Transformer-Based Quadrature Voltage-Controlled Oscillator with a Capacitor Coupling Technique in 90 nm Complementary Metal Oxide Semiconductor," Japanese Journal of Applied Physics, Vol. 51, 04DE04, pp. 1-6, April 2012.
  15. Dayang Nur Salmi Dharmiza, Mototada Oturu, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "An Inverter-Based Wideband Low-Noise Amplifier in 40 nm Complementary Metal Oxide Semiconductor," Japanese Journal of Applied Physics, Vol. 51, 04DE07, pp. 1-5, April 2012.
  16. Sang yeop Lee, Hiroyuki Ito, Shuhei Amakawa, Satoru Tanoi, Noboru Ishihara, and Kazuya Masu, "1.2-17.6 GHz Ring-Oscillator-Based Phase-Locked Loop with Injection Locking in 65 nm Complementary Metal Oxide Semiconductor," Japanese Journal of Applied Physics, Vol. 51, 02BE03, February 2012.
  17. Hamid Kiumarsi, Yutaka Mizuochi, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A Three-Stage Inverter-Based Stacked Power Amplifier in 65 nm Complementary Metal Oxide Semiconductor Process," Japanese Journal of Applied Physics, Vol. 51, 02BC01, February 2012.
  18. 益 一哉，天川 修平，伊藤 浩之，石原 昇， "RF CMOS集積回路技術における挑戦," 電子情報通信学会誌, 第94巻, 第5号, pp. 427-432, 2011年5月.
  19. Hiroyuki Ito, Makoto Kimura, Kazuya Miyashita, Takahiro Ishii, Kenichi Okada, and Kazuya Masu, "A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications," IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, pp. 1020-1029, April 2008.
  20. Kazuma Ohashi, Tackya Yammouch, Makoto Kimura, Hiroyuki Ito, Kenichi Okada, Kazuhisa Itoi, Masakazu Sato, Tatsuya Ito, Ryozo Yamauchi, and Kazuya Masu, "On-Chip Yagi-Uda Antenna for Horizontal Wireless Signal Transmission in Stacked Multi Chip Packaging," Japanese Journal of Applied Physics, Vol. 46, No. 4B, pp. 2283-2286, April 2007.
  21. Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, Tatsuya Ito, Kazuhisa Itoi, Masakazu Sato, Ryozo Yamauchi, and Kazuya Masu, "Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology," IEICE Transactions on Electronics, Vol. E90-C, No.3, pp. 641-643, March 2007.
  22. Kenichi Okada, Hirotaka Sugawara, Hiroyuki Ito, Kazuhisa Itoi, Masakazu Sato, Hiroshi Abe, Tatsuya Ito, and Kazuya Masu, "On-Chip High-Q Variable Inductor Using Wafer-Level Chip-Scale Package Technology," IEEE Transactions on Electron Devices, Vol. 53, No. 9, pp. 2401-2406, September 2006.
  23. Kazuya Masu, Kenichi Okada, and Hiroyuki Ito, "RF Passive Components Using Metal Line on Si CMOS (Invited Paper)," IEICE Transactions on Electronics, Vol. E89-C, No. 6, pp. 681-691, June 2006.
  24. Makoto Kimura, Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu, "Zero-Crosstalk Bus Line Structure for Global Interconnects in Si ULSI," Japanese Journal of Applied Physics, Vol. 45, No. 6A, pp. 4977-4981, June 2006.
  25. Hiroyuki Ito, Shinichiro Gomi, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu, "Twisted Differential Transmission Line Structure for Global Interconnect in Si LSI," Japanese Journal of Applied Physics, Vol. 44, No. 4B, pp. 2774-2777, April 2005.
  26. Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, and Kazuya Masu, "Wide Tuning Range LC-VCO Using Variable Inductor for Reconfigurable RF Circuit," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E88-A, No. 2, pp. 507-512, February 2005.
  27. Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, and Kazuya Masu, "Inductance-Tuned LC-VCO for Reconfigurable RF Circuit Design," IEICE Electronics Express, Vol. 1, No. 7, pp. 156-159, February 2004.
  28. Hiroyuki Ito, Kenichi Okada, and Kazuya Masu, "High Density Differential Transmission Line Structure on Si ULSI," IEICE Transactions on Electronics, Vol. E87-C, No.6, pp. 942-948, June 2004.
  29. Hirotaka Sugawara, Yoshisato Yokoyama, Shinichiro Gomi, Hiroyuki Ito, Kenichi Okada, Hiroaki Hoshino, Hidetoshi Onodera and Kazuya Masu, "Variable RF Inductor on Si CMOS Chip," Japanese Journal of Applied Physics, Vol. 43, No. 4B, pp. 2293-2296, April 2004.
International Conferences
  1. Daisuke Yamane, Toshifumi Konishi, Motohiro Takayasu, Hiroyuki Ito, Shiro Dosho, Noboru Ishihara, Hiroshi Toshiyoshi, Kazuya Masu, and Katsuyuki Machida, "A Sub-1G CMOS-MEMS Accelerometer," IEEE Sensors 2015, pp. 513-516, Nov. 1-4, 2015.
  2. Toshifumi Konishi, Daisuke Yamane, Motohiro Takayasu, Hiroyuki Ito, Shiro Dosho, Noboru Ishihara, Kazuya Masu, Hiroshi Toshiyoshi, and Katsuyuki Machida, "Novel Gain-Controlled Sensor Circuits Designed by Multi-physics Simulation for CMOS-MEMS Accelerometer," International Conference on Solid State Devices and Materials (SSDM 2015), pp. 798-799, Sept. 27-30, 2015.
  3. Hiroyuki Ito, Atsushi Shirane, Noboru Ishihara and Kazuya Masu, "An Ultra-Low-Power 32QAM RF Transmitter," IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), pp. 16-18, 2015. (Invited)
  4. Hiroyuki Ito, Atsushi Shirane, Sho Ikeda, Yosuke Ishikawa, Noboru Ishihara and Kazuya Masu, "Ultra-Low-Power RF Transceiver Technology for Sensor Network Application," The 6th International Conference on Integrated Circuits, Design, and Verification, 2015. (Invited)
  5. Motohiro Takayasu, Toshiaki Gonda, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, " An RF Universal Board for SSOP Elements," Vietnam-Japan Microwave (VJMW), Aug. 10-11, 2015.
  6. Motohiro Takayasu, Toshiaki Gonda, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "An RF Universal Board for SSOP Elements," Thailand-Japan MicroWave (TJMW), Aug. 6-8, 2015.
  7. Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "Ultra-low power wireless transceiver systems for biomedical application," International Conference on Integrative Biology, p. 88, Aug. 4-6, 2015.(invited)
  8. Minami Teranishi, Tso-Fu Mark Chang, Toshifumi Konishi, Takaaki Matsushima, Katsuyuki Machida, Hiroshi Toshiyoshi, Daisuke Yamane, Hiroyuki Ito, Kazuya Masu, Tatsuo Sato, Masato Sone, "Stability of Movable Structure Formed by Au Electroplating for MEMS Devices," 8th Int. Conf. on Materials for Advanced Technologies (ICMAT 2015), June 28 - July 3, 2015.
  9. Yosuke Ishikawa, Sang_yeop Lee, Shin Yonezawa, Sho Ikeda, Yiming Fang, Taisuke Hamada, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu, "A 0.5-V 1.56-mW 5.5-GHz RF Transceiver IC Module with J-Shaped Folded Monopole Antenna," IEEE International Symposium on Circuits and Systems (ISCAS), pp.1218-1221, May 24, 2015.
  10. Atsushi Shirane, Haowei Tan, Yiming Fang, Taiki Ibe, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu, "5.8GHz RF-Powered Transceiver with a 113uW 32-QAM Transmitter Employing the IF-based Quadrature Backscattering Technique" IEEE International Solid-State Circuits Conference (ISSCC2015), pp. 24-25, Feb. 22-26, 2015.
  11. Sho Ikeda, Sang_yeop Lee, Shin Yonezawa, Yiming Fang, Motohiro Takayasu, Taisuke Hamada, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu, "A 0.5-V 5.8-GHz Low-Power Asymmetrical QPSK/OOK Transceiver for Wireless Sensor Network," IEEE/ACM 20th Asia South Pacific Design Automation Conference, pp. 40-41, Jan. 19-22, 2015.
  12. Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "Ultra-Low Power RF Circuit Technology for Wireless Sensor Networks," Thailand-Japan MicroWave (TJMW), TH1-1_69720, Nov. 26-28, 2014. (Invited)
  13. Taisuke Hamada, Hao Jiang, Yiming Fang, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A 0.5-V 2.5-GHz High-Gain Low-Power Regenerative Amplifier Based on Colpitts Oscillator Topology in 65-nm CMOS," 2014 IEEE Asia Pacific Conferences on Circuits and Systems, ANA Intercontinental Ishigaki Resort Hotel, Okinawa, Japan, pp. 340-343, Nov. 17-20, 2014.
  14. Hiroyuki Ito, Shoichi Masui, Youichi Momiyama, Yoshihiro Yoneda, Taiki Ibe, Taisuke Hamada, Noboru Ishihara, and Kazuya Masu, "An Ultra-Low-Power RF Transceiver with a 1.5-pJ/bit Maximally-Digital Impulse-Transmitter and an 89.5-μW Super-Regenerative RSSI," IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 265-268, 2014.
  15. Sho Ikeda, Sang-yeop Lee, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A 0.52-V 5.7-GHz Low Noise Sub-Sampling PLL with Dynamic Threshold MOSFET," IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 365-368, 2014.
  16. Sho Ikeda, Sang_yeop Lee, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A 0.5-V 5.8-GHz Highly Linear VCO with Back-Gate Tuning Technique," in Proc. Int. Conf. on Solid-State Devices and Materials (SSDM 2014), Tsukuba International Congress Center, Tsukuba, Japan, pp. 984-985, Sep. 8-11, 2014.
  17. Hiroyuki Ito, Shoichi Masui, Youichi Momiyama, Atsushi Shirane, Motohiro Takayasu, Yoshihiro Yoneda, Taiki Ibe, Taisuke Hamada, Sho Ikeda, Daisuke Yamane, Noboru Ishihara, and Kazuya Masu, "2.3 pJ/bit Frequency-Stable Impulse OOK Transmitter Powered Directly by an RF Energy Harvesting Circuit with -19.5 dBm Sensitivity," IEEE Radio Frequency Integrated Circuits Symposium, Tampa Convention Center, USA, pp. 13-15, Jun. 1-3, 2014.
  18. Sho Ikeda, Sang_yeop Lee, Shin Yonezawa, Yiming Fang, Motohiro Takayasu, Taisuke Hamada, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A 0.5-V 5.8-GHz Ultra-Low-Power RF Transceiver for Wireless Sensor Network in 65nm CMOS," IEEE Radio Frequency Integrated Circuits Symposium, Tampa Convention Center, USA, pp. 29-32, Jun. 1-3 , 2014.
  19. Sho Ikeda, Tatsuya Kamimura, Sangyeop Lee, Hiroyuki Ito, Noboru Ishihara and Kazuya Masu, "A 950uW 5.5-GHz Low Voltage PLL with Digitally-Calibrated ILFD and Linearized Varactor," The 19th Asia and South Pacific Design Automation Conference, Suntec Convention Center, Singapore, pp. 23-24, Jan. 21, 2014.
  20. Daisuke Yamane, Toshifumi Konishi, Takaaki Matsushima, Gou Motohashi, Ken Kagaya, Hiroyuki Ito, Noboru Ishihara, Hiroshi Toshiyoshi, Katsuyuki Machida, and Kazuya Masu, "Sub-1G MEMS Accelerometer," IEEE SENSORS 2013, pp. 171-174, 2013,
  21. Sho Ikeda, Tatsuya Kamimura, Sang yeop Lee, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A Transformer-Based Current-Reuse QVCO with a Capacitor Coupling Technique in 180 nm CMOS," IEEE European Microwave Integrated Circuits Conference 2013 (EuMIC2013), pp. 93-96, 2013.
  22. Motohiro Takayasu, Atsushi Shirane, Sangyeop Lee, Daisuke Yamane, Hiroyuki Ito, Mi Xiaoyu, Hiroaki Inoue, Fumihiko Nakazawa, Satoshi Ueda, Noboru Ishihara, and Kazuya Masu, "An 8-ch, 20-V Output CMOS Switching Driver with 3.3-V Power Supply for Integrated MEMS Devices Controlling," 2013 Int. Conf. on Solid State Devices and Materials (SSDM 2013), PS-5-1, 2013.
  23. Toshifumi Konishi, Daisuke Yamane, Takaaki Matsushima, Satoshi Maruyama, Ken Kagaya, Hiroyuki Ito, Noboru Ishihara, Hiroshi Toshiyoshi, Katsuyuki Machida, and Kazuya Masu, "Novel Sensor Circuits Design Using Multi-physics Simulation for CMOS-MEMS Technology," 2013 Int. Conf. on Solid State Devices and Materials (SSDM 2013), G-4-2, 2013.
  24. Daisuke Yamane, Toshifumi Konishi, Takaaki Matsushima, Gou Motohashi, Ken Kagaya, Hiroyuki Ito, Noboru Ishihara, Hiroshi Toshiyoshi, Katsuyuki Machida, and Kazuya Masu, "AN ARRAYED MEMS ACCELEROMETER WITH A WIDE RANGE OF DETECTION," in Proc. 17th Int. Conf on Solid-State Sensors, Actuators and Microsystems (Transducers 2013), pp. 22-25, 2013.
  25. Sho Ikeda, Tatsuya Kamimura, Sang yeop Lee, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A Sub-1mW 5.5-GHz PLL with Digitally-Calibrated ILFDand Linearized Varactor for Low Supply Voltage Operation," IEEE Radio Frequency Integrated Circuit 2013 (RFIC), pp. 439-442, 2013.
  26. Sho Ikeda, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "Optimal Design Method for Chip-Area-Efficient CMOS Low-Dropout Regulator," 2012 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 332-335, 2012.
  27. Sho Ikeda, Tatsuya Kamimura, Sang yeop Lee, Norifumi Kanemaru, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A 0.5-V 5.5-GHz Class-C-VCO-Based PLL with Ultra-Low-Power ILFD in 65 nm CMOS," IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 357-360, 2012.
  28. Sho Ikeda, Sang yeop Lee, Tatsuya Kamimura, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "Fractionally Injection-Locked Frequency Multiplication Technique with Multi-Phase Ring VCO," 2012 Int. Conf. on Solid State Devices and Materials (SSDM), pp. 1158-1159, 2012.
  29. Daisuke Yamane, Takaaki Matsushima, Toshifumi Konishi, Gou Motohashi, Hiroyuki Ito, Noboru Ishihara, Hiroshi Toshiyoshi, Katsuyuki Machida, and Kazuya Masu, "A Novel Sensor Structure and its Fabrication Process for Integrated CMOS-MEMS Accelerometer," 2012 Int. Conf. on Solid State Devices and Materials (SSDM), pp. 1134-1135, 2012.
  30. Toshifumi Konishi, Satoshi Maruyama, Makoto Mita, Daisuke Yamane, Hiroyuki Ito, Katsuyuki Machida, Noboru Ishihara, Kazuya Masu, Hiroyuki Fujita, and Hiroshi Toshiyoshi, "A CMOS-MEMS Design Technique based on an Electrical Circuit Simulator with Hardware Description Language," 2012 Int. Conf. on Solid State Devices and Materials (SSDM), pp. 1120-1121, 2012.
  31. Sang yeop Lee, Sho Ikeda, Hiroyuki Ito, Satoru Tanoi, Noboru Ishihara, and Kazuya Masu, "An Inductorless Injection-Locked PLL with 1/2- and 1/4-Integral Subharmonic Locking in 90 nm CMOS," IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 189-192, 2012.
  32. Atsushi Shirane, Mototada Otsuru, Sang yeop Lee, Shin Yonezawa, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A Process-Scalable RF Transceiver for Short Range Communication in 90 nm Si CMOS," IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 455-458, 2012.
  33. Atsushi Shirane, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A Study on Integration of MEMS and CMOS with Applying Flip-chip Assembly in Wireless Applications," Materials Research Society Spring Meeting, 2012.
  34. Hamid Kiumarsi, Hiroyuki Ito, Noboru Ishihara, Kenichi Okada, Yusuke Uemichi, Yasuto Chiba, and Kazuya Masu, "A 3-dB Quadrature WLP Coupler for 60 GHz Applications", Materials Research Society Spring Meeting, 2012.
  35. Atsushi Shirane, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A 21V Output Charge Pump Circuit with Appropriate Well-Bias Supply Technique in 0.18 um Si CMOS," International SoC Design Conference 2011 (ISOCC2011), pp. 28-31, 2011.
  36. Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Sang yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A Ring-VCO-Based Injection-Locked Frequency Multiplier Using a New Pulse Generation Technique in 65 nm CMOS," International SoC Design Conference 2011 (ISOCC2011), pp. 32-35, 2011.
  37. Dayang Nur Salmi Dharmiza, Mototada Oturu, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "An Inverter-based Wideband Low Noise Amplifier in 40nm CMOS Process," Extended Abstracts of the 2011 International Conference on Solid State Devices and Materials (SSDM), pp. 1083-1084, 2011.
  38. Sang yeop Lee, Hiroyuki Ito, Shuhei Amakawa, Satoru Tanoi, Noboru Ishihara, and Kazuya Masu, "1.2-17.6 GHz Ring-VCO-Based PLL with Injection Locking in 65 nm CMOS," Extended Abstracts of the 2011 International Conference on Solid State Devices and Materials (SSDM), pp. 1063-1064, 2011.
  39. Tatsuya Kamimura, Sang yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A 0.1-V 13-GHz Transformer-Based Quadrature VCO with a Capacitor Coupling Technique in 90nm CMOS," Extended Abstracts of the 2011 International Conference on Solid State Devices and Materials (SSDM), pp. 1061-1062, 2011.
  40. Hamid Kiumarsi, Yutaka Mizuochi, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A Stacked Inverterbased CMOS Power Amplifier in 65nm CMOS Process," Extended Abstracts of the 2011 International Conference on Solid State Devices and Materials (SSDM), pp. 831-832, 2011.
  41. Atsushi Shirane, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "RF MEMS Planar Solenoidal Inductor with Wide Tunability," Advanced Metallization Conference (AMC), p. 47, 2011; ADMETA plus 2011: Asian Session, pp. 74-75, 2011.
  42. Hiroyuki Ito, Hiroyuki Nakamoto, Masahiro Kudo, Nobuhiko Kobayashi, Masazumi Marutani, and Daisuke Yamazaki, "Local Quadrature Signal and Carrier Leakage Calibration Techniques for a Mobile-WiMAX Transceiver," IEEE International Conference on Wireless Information Technology and Systems, Session 206.2, 2010.
  43. Hiroyuki Nakamoto, Masahiro Kudo, Hiroyuki Ito, and Daisuke Yamazaki, "A Carrier Leakage Auto-Calibration Circuit with a Direct DC-Offset Comparison Technique for a WiMAX Transmitter," IEEE Symposium on VLSI Circuits, pp. 91-92, 2010.
  44. Shuhei Amakawa, Koh Yamanaga, Hiroyuki Ito, Takashi Sato, Noboru Ishihara, and Kazuya Masu, "S-Parameter Based Modal Decomposition of Multiconductor Transmission Lines and Its Application to De-Embedding," International Conference on Microelectronic Test Structures (ICMTS), pp. 177-180, 2009.
  45. Akiko Mineyama, Toshihide Suzuki, Hiroyuki Ito, Shuhei Amakawa, Noboru Ishihara, and Kazuya Masu, "A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90 nm CMOS Process," IEEE MTT-S International Workshop Series on Signal Integrity and High-Speed Interconnects (IMWS2009-R9), pp. 119-122, 2009.
  46. Kazuya Miyashita, Takahiro Ishii, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "An Over-12-Gbps On-Chip Transmission Line Interconnect with a Pre-Emphasis Technique in 90 nm CMOS," 17th Conference on Electrical Performance of Electronic Packaging (EPEP), pp. 303-306, 2008.
  47. Hideki Hatakeyama, Yusuke Uemichi, Kazuma Ohashi, Satoshi Fukuda, Hiroyuki Ito, Kenichi Okada, Takuya Aizawa, Tatsuya Ito, and Kazuya Masu, "RF CMOS Circuits with Wafer-Level Packaging Inductors," International Wafer-Level Packaging Conference, pp. 69-73, 2008.
  48. Shuhei Amakawa, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, "A Simple De-Embedding Method for Characterization of On-Chip Four-Port Networks," Advanced Metallization Conference (AMC), 2008.
  49. Hiroyuki Ito, Hasnain Lakdawala, Ashoke Ravi, Stefano Pellerano, Richard Ruby, K. Soumyanath, and Kazuya Masu, "A 1.7-GHz 1.5-mW Digitally-Controlled FBAR Oscillator with 0.03-ppb Resolution," the 34th European Solid-State Circuits Conference (ESSCIRC), pp. 98-101, 2008.
  50. Tomoaki Maekawa, Hiroyuki Ito, and Kazuya Masu, "An 8Gbps 2.5mW On-Chip Pulsed-Current-Mode Transmission Line Interconnect with a Stacked-Switch Tx," the 34th European Solid-State Circuits Conference (ESSCIRC), pp. 474-477, 2008.
  51. Susumu Sadoshima, Satoshi Fukuda, Hiroyuki Ito, Kazuhisa Itoi, Masakazu Sato, Tatsuya Ito, Ryozo Yamauchi, Kenichi Okada, Noboru Ishihara, and Kazuya Masu, "A 2-GHz-band CMOS Low Noise Amplifier with High-Q Inductors Embedded in Wafer-Level Package," International Conference on Solid State Devices and Materials (SSDM), pp. 74-75, 2008.
  52. Hiroyuki Ito and Kazuya Masu, "A Simple Through-Only De-Embedding Method for On-Wafer S-Parameter Measurements up to 110 GHz," IEEE MTT-S International Microwave Symposium (IMS), pp. 383-386, 2008.
  53. Kazuma Ohashi, Yuka Kobayashi, Hiroyuki Ito, Kenichi Okada, Hideki Hatakeyama, Takuya Aizawa, Tatsuya Ito, Ryozo Yamauchi, and Kazuya Masu, "A Low Phase Noise LC-VCO with a High-Q Inductor Fabricated by Wafer Level Package Technology," IEEE RFIC Symposium, pp. 123-126, 2008.
  54. Tomoaki Maekawa, Takahiro Ishii, Junki Seita, Hiroyuki Ito, Kenichi Okada, Hideki Hatakeyama, Yusuke Uemichi, Takuya Aizawa, Tatsuya Ito, Ryozo Yamauchi, and Kazuya Masu, "A Low-Power Differential Transmission Line Interconnect using Wafer Level Package Technology," IEEE Workshop on Signal Propagation on Interconnects (SPI), 2008.
  55. Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu, "LVDS-type On-Chip Transmission Line Interconnect with Passive Equalizers in 90 nm CMOS Process," IEEE/ACM Asia and South Pacific Design Automation Conference (University LSI Design Contest), pp. 97-98, 2008.
  56. Susumu Sadoshima, Satoshi Fukuda, Tackya Yammouch, Hiroyuki Ito, Kenichi Okada, and Kazuya Masu, "Small-Area CMOS RF Distributed Mixer Using Multi-Port Inductors," IEEE/ACM Asia and South Pacific Design Automation Conference (University LSI Design Contest), pp. 105-106, 2008.
  57. Kazuma Ohashi, Yusaku Ito, Hiroyuki Ito, Kenichi Okada, Hideki Hatakeyama, Naoyuki Ozawa, Masakazu Sato, Takuya Aizawa, Tatsuya Ito, Ryozo Yamauchi, and Kazuya Masu, "A Low-Power Low-Phase-Noise CMOS VCO using RF SiP Technology," Asia-Pacific Microwave Conference (APMC), pp. 1777-1780, 2007.
  58. Satoshi Fukuda, Hiroyuki Ito, Kazuhisa Itoi, Masakazu Sato, Tatsuya Ito, Ryozo Yamauchi, Kenichi Okada, and Kazuya Masu, "A 5.2GHz CMOS Low Noise Amplifier with High-Q Inductors Embedded in Wafer-Level Chip-Scale Package," International Workshop on RF Integration Technology (RFIT), pp. 34-37, 2007.
  59. Kazuya Miyashita, Hiroyuki Ito, Kenichi Okada, and Kazuya Masu, "High Frequency Characteristics of On-Chip Wirings up to 110 GHz," Advanced Metallization Conference (AMC), pp.103-104, 2007; Advanced Metallization Conference, Asian Session (ADMETA), pp. 106-107, 2007.
  60. Shuhei Amakawa, Hiroyuki Ito, and Kazuya Masu, "Signal Transmission Through Interconnects with Repetitive Loads," Advanced Metallization Conference (AMC), pp.173-174, 2007; Advanced Metallization Conference, Asian Session (ADMETA), pp. 94-95, 2007.
  61. Yuka Kobayashi, Kazuma Ohashi, Yusaku Ito, Hiroyuki Ito, Kenichi Okada, and Kazuya Masu, "A 0.49-6.50GHz Wideband LC-VCO with High-IRR in a 180 nm CMOS Technology," International Conference on Solid State Devices and Materials (SSDM), pp. 268-269, 2007.
  62. Hiroyuki Ito, Makoto Kimura, Kenichi Okada, and Kazuya Masu, "A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission Line Interconnect with 1.2-mW Two-Way Transceivers," IEEE Symposium on VLSI Circuits, pp. 136-137, 2007.
  63. Hiroyuki Ito, Junki Seita, Takahiro Ishii, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu, "A Low-Latency and High-Power-Efficient On-Chip LVDS Transmission Line Interconnect for an RC Interconnect Alternative," IEEE International Interconnect Technology Conference (IITC), pp. 193-195, 2007.
  64. Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, and Kazuya Masu, "A Multi-Drop Transmission-Line Interconnect in Si LSI," IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), pp. 118-119, 2007.
  65. Takahiro Ishii, Hiroyuki Ito, Makoto Kimura, Kenichi Okada, and Kazuya Masu, "A 6.5-mW 5-Gbps On-Chip Differential Transmission Line Interconnect with a Low-Latency Asymmetric Tx in a 180nm CMOS Technology," IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 131-134, 2006.
  66. Kenichi Okada, Hiroyuki Ito, and Kazuya Masu, "On-Chip Differential-Transmission-Line(DTL) Interconnect for 22nm Technology," Advanced Metallization Conference (AMC), pp. 2-3, 2006; Advanced Metallization Conference, Asian Session (ADMETA), pp. 124-125, 2006; MRS Proceedings: Advanced Metallization Conference (AMC), pp. 29-33, 2006.
  67. Kazuya Masu, Kenichi Okada, and Hiroyuki Ito, "Transmission Line Interconnect on Si CMOS LSI (Invited Paper)," International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), pp. 306-309, 2006.
  68. Makoto Kimura, Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu, "High-Crosstalk Robustness Transmission Line Interconnect in Si LSI using Zero-Crosstalk Structure," IEEE Workshop on Signal Propagation on Interconnects (SPI), pp. 153-156, 2006.
  69. Hiroyuki Ito, Kenichi Okada, and Kazuya Masu, "A Loss Optimization Method Using WD Product for On-Chip Differential Transmission Line Design," IEEE Workshop on Signal Propagation on Interconnects (SPI), pp. 217-220, 2006.
  70. Kazuya Masu, Kenichi Okada, and Hiroyuki Ito, "On-chip signal transmission and interconnect for Si CMOS LSI (Invited Paper)," IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), pp. 353-356, 2006.
  71. Junki Seita, Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, Tatsuya Ito, Kazuhisa Itoi, Masakazu Sato, and Kazuya Masu, "Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology for One-Chip Wireless Communication Circuits," IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), pp. 338-341, 2006.
  72. Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu, "4 Gbps On-Chip Interconnection using Differential Transmission Line," IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 417-420, 2005.
  73. Makoto Kimura, Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu, "High-Density Differential Transmission Line Bus Structure for 65nm Technology," Advanced Metallization Conference (AMC), pp. 26-27, 2005; Advanced Metallization Conference Asian Session (ADMETA), pp. 56-57, 2005; MRS Proceedings: Advanced Metallization Conference (AMC), pp. 143-149, 2005.
  74. Makoto Kimura, Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu, "Zero-Crosstalk Bus Line Structure for Global Interconnects in Si ULSI," International Conference on Solid State Devices and Materials (SSDM), pp. 936-937, 2005.
  75. Hideyuki Sugita, Hiroyuki Ito, Shinichiro Gomi, Kenichi Okada, and Kazuya Masu, "On-Wafer Measurement of Pseudo Differential Transmission Line for Global Interconnect in Si LSI," International Meeting for Future of Electron Devices (IMFEDK), pp. 35-36, 2005.
  76. Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, and Kazuya Masu, "Evaluation of On-Chip Transmission Line Interconnect Using Wire Length Distribution," IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), pp. 133-138, 2005.
  77. Hiroyuki Ito, Junpei Inoue, Shinichiro Gomi, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu, "On-Chip Transmission Line for Long Global Interconnects," IEEE International Electron Devices Meeting (IEDM), pp. 677-680, 2004.
  78. Hiroyuki Ito, Shinichiro Gomi, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu, "High Density Bus Line Structure With Pseudo Differential Transmission Line in Si ULSI," IEEE Asia-Pacific Microwave Conference (APMC), p. 175, 2004.
  79. Shinichiro Gomi, Kohichi Nakamura, Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu, "High Speed and Low Power On-Chip Micro Network Circuit with Differential Transmission Line," IEEE International Symposium on System-on-Chip, pp. 173-176, 2004.
  80. Hideyuki Sugita, Hiroyuki Ito, Shinichiro Gomi, Kenichi Okada, and Kazuya Masu, "Pseudo Differential Transmission Line Structure on Si ULSI," Advanced Metallization Conference (AMC), pp. 84-85, 2004; Advanced Metallization Conference Asian Session (ADMETA), pp. 126-127, 2004; MRS Proceedings: Advanced Metallization Conference (AMC), pp. 165-170, 2004.
  81. Hirotaka Sugawara, Yoshiaki Yoshihara, Hiroyuki Ito, Kenichi Okada, and Kazuya Masu, "Wide-Range RF Variable Inductor on Si CMOS Chip with MEMS Actuator," IEEE European Microwave Conference (EuMC), pp. 701-704, 2004.
  82. Shinichiro Gomi, Kohichi Nakamura, Hiroyuki Ito, Kenichi Okada, and Kazuya Masu, "Differential Transmission Line Interconnect for High Speed and Low Power Global Wiring," IEEE Custom Integrated Circuits Conference (CICC), pp. 325-328, 2004.
  83. Masakazu Sato, Kazuhisa Itoi, Hiroshi Abe, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu, and Tatsuya Ito, "On-chip Spiral Inductors Integrated with Wafer-Level Package," International Conference on Solid State Devices and Materials (SSDM), pp. 286-287, 2004.
  84. Hiroyuki Ito, Shinichiro Gomi, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu, "Twisted Differential Transmission Line Structure for EMI Noise Reduction at Global Interconnect in Si LSI," International Conference on Solid State Devices and Materials (SSDM), pp. 290-291, 2004.
  85. Shinichiro Gomi, Kohichi Nakamura, Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu, "High-Speed Transmission Circuit for Micro-Network on Si ULSI," International Conference on Solid State Devices and Materials (SSDM), pp. 308-309, 2004.
  86. Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuhisa Itoi, Masakazu Sato, Hiroshi Abe, Tatsuya Ito, and Kazuya Masu, "High-Q Variable Inductor Using Redistributed Layers for Si RF Circuits," IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), pp. 187-190, 2004.
  87. Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, and Kazuya Masu, "A Wide Tuning Range CMOS VCO using Variable Inductor," IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), pp. 278-281, 2004.
  88. Shinichiro Gomi, Kohichi Nakamura, Hiroyuki Ito, Kenichi Okada, and Kazuya Masu, "High Speed and Low Power Global Interconnect IP with Differential Transmission Line and Driver-Receiver Circuits," IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC), pp. 384-387, 2004.
  89. Hiroyuki Ito, Shinichiro Gomi, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu, "Differential Transmission Line Structure for Over 10 Gbps Signal Transmission at Global Interconnect in Si ULSI," IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Designer Forum (AP-ASIC), pp. 414-415, 2004.
  90. Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, and Kazuya Masu, "Reconfigurable RF Circuit Design for Multi-band Wireless Chip," IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Designer Forum (AP-ASIC), pp. 418-419, 2004.
  91. Kazuhisa Itoi, Masakazu Sato, Hiroshi Abe, Hiroyuki Ito, Hirotaka Sugawara, Kenichi Okada, Kazuya Masu, and Tatsuya Ito, "On-chip High-Q Solenoid Inductors Embedded in WL-CSP," IEEE Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, pp. 105-108, 2004.
  92. Kazuhisa Itoi, Masakazu Sato, Hiroshi Abe, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu, and Tatsuya Ito, "On-Chip High-Q Cu Inductors Embedded In Wafer-Level Chip-Scale Package for Silicon RF Application," IEEE MTT-S International Microwave Symposium (IMS), pp. 197-200, 2004.
  93. Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, and Kazuya Masu, "Wide Tunable LCVCO using Variable Inductor," IEEE Workshop on Wireless Circuits and Systems (WoWCAS), pp. 29-30, 2004.
  94. Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, and Kazuya Masu, "Modeling for Variable RF Inductor on Si CMOS Chip," International Workshop on Compact Modeling (IWCM), pp. 24-28, 2004.
  95. Hiroyuki Ito, Kenichi Okada and Kazuya Masu, "Low Crosstalk Bus Line Configuration Using Differential Transmission Line Interconnect on Si ULSI," IEEE Asia-Pacific Microwave Conference (APMC), No.2 pp. 1006-1009, 2003.
  96. Hiroyuki Ito, Shinichiro Gomi, Hirotaka Sugawara, Kenichi Okada, and Kazuya Masu, "Low Crosstalk Differential Transmission Line Interconnect on Si ULSI," Advanced Metallization Conference (AMC), pp. 9-10, 2003; Advanced Metallization Conference, Asian Session (ADMETA), pp. 56-57, 2003; MRS Proceedings: Advanced Metallization Conference (AMC), pp. 53-58, 2003.
  97. Shinichiro Gomi, Yoshisato Yokoyama, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Hiroaki Hoshino, Hidetoshi Onodera, and Kazuya Masu, "Variable RF Inductor on Si CMOS Chip," International Conference on Solid State Devices and Materials (SSDM), pp. 398-399, 2003.
  98. Hiroyuki Ito, Hiyouko Shinoki, Yoshisato Yokoyama, and Kazuya Masu, "Transmission Line Interconnect Structure in Si ULSI," Advanced Metallization Conference, Asian Session (ADMETA), pp. 78-79, 2002; MRS Proceedings: Advanced Metallization Conference (AMC), pp. 297-302, 2002.
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